The present invention relates generally to output drivers and operation modes for integrated circuit devices, and in particular, the present invention relates to output drivers and operation modes to selectively disable outputs of an integrated circuit memory device.
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes integrated circuit memory devices.
Integrated circuit memory devices are rapidly-accessible memory devices. In an integrated circuit memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Integrated circuit memory devices typically store information in a large array of cells. Data and status information of the memory device are provided to external devices through a set of DQ or data lines.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of integrated circuit memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment use flash memory cards as the medium to store data, send and receive wireless faxes, and store digital audio clips and digital images. Each of these applications requires large amounts of highly reliable memory.
Memory devices are generally fabricated on semiconductor wafers. Each of these wafers typically contains a number of individual integrated circuit memory devices formed in rectangular areas known as dies. After fabrication, each die is separated, or diced, then packaged in a format suitable for the end user.
Before or after dicing and packaging, a manufacturer may test its integrated circuit devices as part of a quality program to improve end-use reliability. such tests are generally performed on highly-specialized testing systems or tester hardware. Prior to dicing, tests may be performed by the testing system on each die of a semiconductor wafer in pattern. The tester hardware may test each die individually or it may test multiple dies concurrently. Subsequent to dicing, tests may be performed by the testing system on multiple packaged components in pattern. The tester hardware may test each component individually or it may test multiple components concurrently. The die or component being tested is often referred to as a device under test (DUT).
In general, signals and potentials are applied to or received from the DUT through a set of leads often referred to as probes or contractors. These leads may be individually located to the appropriate landing pad or pin on the DUT or they may grouped as a part of a head, card or module used to locate multiple leads simultaneously.
Some memory devices provide one or more status bits indicating when or if an operation performed on the device is completed successfully. After initiating an operation, one or more of these status bits are polled for the indication of completion. If a memory device indicates failure of the operation, such as a read, write or erase operation, it may be desirable to deem the device as failed and to discontinue testing of the device rather than continue to write or erase potentially millions of device addresses after deeming the device as failed. This can be accommodated by exiting the tester pattern, disabling the device in tester hardware, and re-entering the tester pattern. However, this can be a time-consuming and disruptive process, thus adding to fabrication costs.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate operation modes and integrated circuit devices supporting such operation modes beneficial to device testing.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Output driver stages and operation modes are described herein for selectively disabling outputs of an integrated circuit device, and particularly a memory device, by selectively disabling one or more output drivers. Such output driver stages and operation modes are generally independent of the device architecture. An inhibit signal is provided having a first logic level to facilitate normal operation of the output drivers responsive to a global output enable signal and having a second logic level to disable the output drivers regardless of the global output enable signal. The inhibit signal may be provided directly to one or more output drivers. Alternatively, the inhibit signal may be combined with the global output enable signal. The inhibit signal may be common to all coupled output drivers or a separate inhibit signal may be provided for each such output driver. Selective disabling of output drivers can be used to force a device time-out during testing. Selective disabling of output drivers can also be used to reduce device power requirements.
Various embodiments are adapted to selectively disable the outputs of a memory device without adversely affecting timing characteristics or other operations of the memory device. As an example, despite having an output disabled in accordance with the various embodiments, a memory device may still write to or erase a memory cell, and may still read from a memory cell, albeit without providing the data value on the disabled output.
For one embodiment, the invention provides an integrated circuit device. The device includes a plurality of output drivers including at least one first output driver and at least one second output driver and a logic circuit for providing a first control signal. Each first output driver is responsive to a second control signal when the first control signal has a first logic level and is disabled when the first control signal has a second logic level, regardless of a logic level of the second control signal. Each second output driver is responsive to the second control signal regardless of a logic level of the first control signal.
For another embodiment, the invention provides an integrated circuit device. The device includes a logic circuit for providing at least two first control signals, at least two first output drivers and at least one second output driver. Each first output driver is associated with one of the first control signals. In addition, each first output driver is responsive to a second control signal when its associated first control signal has a first logic level and is disabled when its associated first control signal has a second logic level, regardless of a logic level of the second control signal. Each second output driver is responsive to the second control signal regardless of a logic level of any of the first control signals.
For one embodiment, the invention provides a memory device. The memory device includes a logic circuit for providing an inhibit signal and an output driver stage having at least one output driver. Each output driver is responsive to a global output enable signal when the inhibit signal has a first logic level. Each output driver is disabled when the inhibit signal has a second logic level, regardless of a logic level of the global output enable signal.
For another embodiment, the invention provides a memory device. The memory device includes a logic circuit for providing an inhibit signal and an output driver stage having at least one output driver coupled to receive a global output enable signal on a first control node and the inhibit signal on a second control node. Each output driver is responsive to the global output enable signal when the inhibit signal has a first logic level. Each output driver is disabled when the inhibit signal has a second logic level, regardless of a logic level of the global output enable signal.
For yet another embodiment, the invention provides a method of operating a memory device. The method includes combining an inhibit signal with a global output enable signal, thereby producing a local output enable signal. The method further includes applying the local output enable signal to a control node of at least one output driver of the memory device. The local output enable signal has a logic level indicative of a logic level of the global output enable signal when the inhibit signal has a first logic level. The local output enable signal has a logic level independent of the logic level of the global output enable signal when the inhibit signal has a second logic level.
For still another embodiment, the invention provides a method of operating a memory device. The method includes combining an inhibit signal with a global output enable signal, thereby producing a local output enable signal, and applying the local output enable signal to a control node of at least one output driver of the memory device. The method further includes permitting normal operation of each at least one output driver responsive to a logic level of the global output enable signal when the inhibit signal has a first logic level. The method still further includes disabling each at least one output driver when the inhibit signal has a second logic level regardless of the logic level of the global output enable signal.
For a further embodiment, the invention provides a method of operating a memory device. The method includes latching a mask in a logic circuit for providing a plurality of inhibit signals, providing a global output enable signal to first control nodes of a plurality of output drivers of the memory device, and providing the plurality of inhibit signals to second control nodes of the plurality of output drivers in a one-to-one relationship. The method further includes permitting normal operation of an output driver responsive to a logic level of the global output enable signal when the inhibit signal associated with the output driver has a first logic level. The method still further includes disabling an output driver when the inhibit signal associated with the output driver has a second logic level regardless of the logic level of the global output enable signal.
For a still further embodiment, the invention provides a method of testing a memory device. The method includes tri-stating a first portion of output drivers of the memory device in response to detecting a failure of an access operation on the memory device and permitting normal operation of the remaining output drivers while the first portion of output drivers is tri-stated.
For another embodiment, the invention provides a method of testing a memory device. The method includes tri-stating a first portion of output drivers of the memory device corresponding to xe2x80x9cdon""t carexe2x80x9d bits and permitting normal operation of the remaining output drivers while the first portion of output drivers is tri-stated.
For yet another embodiment, the invention provides a method of testing a memory device. The method includes performing an access operation on the memory device and detecting a failure of the access operation. The method further includes providing an inhibit signal to a first portion of output drivers of the memory device subsequent to detecting the failure of the access operation, thereby tri-stating each output driver of the first portion of output drivers. The method still further includes isolating a remaining portion of output drivers of the memory device from the inhibit signal and polling at least one output driver of the remaining portion of output drivers for a ready condition. The method still further includes attempting to access at least one output driver of the tri-stated first portion of output drivers subsequent to detecting the ready condition.
The invention further provides methods and apparatus of varying scope.